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rev. 0.3 / jul. 2013 1 240pin load reduce d ddr3(l) sdram dimm *sk hynix reserves the right to change pr oducts or specifications without notice. ddr3(l) sdram load reduced dimm based on 4gb a-die hmt84gl7amr4a hmt84gl7amr4c
rev. 0.3 / jul. 2013 2 revision history revision no. history draft date remark 0.1 initial release mar.2013 0.2 idd specification update & changed module maximum thickness to reflect the measured maximum jun.2013 0.3 idd update (montage 1.5v 1866mbps) jul.2013
rev. 0.3 / jul. 2013 3 description sk hynix load reduced ddr3(l) sdram dimms are lo w power, high-speed operation memory modules that use sk hynix ddr3(l) sdram devices. these lo ad reduced dimms are inte nded for use as main memory when installed in systems such as servers and workstations. features ? 240 pin load reduced ddr3(l) dr am dual in-line memory module ? buffer performance by lrdimm presenting less load to system ? compatible with rdimm system s with appropriate bios changes ? backward compatible with 1.5v ddr3 memory module ? ordering information * in order to uninstall fdhs, pl ease contact sales administrator part number density organization component composition # of ranks mb fdhs height vendor version hmt84gl7amr4a -h9/pb 32gb 4gx72 ddp 2gx4(h5tc8g43amr)*36 4 montage c1 o 30.35mm inphi gs02b hmt84gl7amr4c -h9/pb/rd ddp 2gx4(h5tq8g43amr)*36 montage c1 inphi gs02b
rev. 0.3 / jul. 2013 4 key parameters * sk hynix dram devices support optional downbinning to cl11, cl9 and cl7. spd setting is programmed to match. speed grade address table mt/s grade tck (ns) cas latency (tck) trcd (ns) trp (ns) tras (ns) trc (ns) cl-trcd-trp ddr3-1066 -g7 1.875 7 13.125 13.125 37.5 50.625 7-7-7 ddr3-1333 -h9 1.5 9 13.5 (13.125)* 13.5 (13.125)* 36 49.5 (49.125)* 9-9-9 ddr3-1600 -pb 1.25 11 13.75 (13.125)* 13.75 (13.125)* 35 48.75 (48.125)* 11-11-11 ddr3-1866 -rd 1.07 13 13.91 (13.125)* 13.91 (13.125)* 34 47.91 (48.125)* 13-13-13 grade frequency [mhz] remark cl6 cl7 cl8 cl9 cl10 cl11 cl12 cl13 -g7 800 1066 1066 -h9 800 1066 1066 1333 1333 -pb 800 1066 1066 1333 1333 1600 -rd 800 1066 1066 1333 1333 1600 1866 32gb(4rx4) refresh method 8k/64ms row address a0-a15 column address a0-a9,a11 bank address ba0-ba2 page size 1kb
rev. 0.3 / jul. 2013 5 pin descriptions pin name description num ber pin name description num ber ck0 clock input, positive line 1 par_in parity bit for the address and con- trol bus 1 ck0 clock input, negative line 1 err_out parity error found on the address and control bus 1 ck1 clock input, positive line 1 od t[0] on die termination inputs 1 ck1 clock input, negative line 1 dq[63:0] data input/output 64 cke[1:0] clock enables 2 cb[7:0] d ata check bits input/output 8 cke[3:2], odt[1], test clock enables on die termination memory bus tool (not con- nected and not useable on dimms) 2dqs[8:0] data strobes 9 ras row address strobe 1 dqs[8:0] data strobes, negative line 9 cas column address strobe 1 dm[8:0]/ dqs[17:9], tdqs[17:9] data masks / data strobes, termination data strobes 9 we write enable 1 dqs[17:9] , tdqs[17:9] data masks / data strobes, termination data strobes 9 s [1:0] chip selects 2 event reserved for optional hardware temperature sensing 1 s[3:2] , a17, a16 chip selects address inputs 2test memory bus test tool (not con- nected and not usable on dimms) 1 a[9:0],a11, a[15:13] address inputs 14 reset register and sdram control pin 1 a10/ap address input/autoprecharge 1 v dd power supply 22 a12/bc address input/burst chop 1 v ss ground 59 ba[2:0] sdram bank addresses 3 v refdq reference voltage for dq 1 scl serial presence detect (spd) clock input 1 v refca reference voltage for ca 1 sda spd data input/output 1 v tt termination voltage 4 sa[2:0] spd address inputs 3 v ddspd spd power 1
rev. 0.3 / jul. 2013 6 input/output functional descriptions symbol type polarity function ck0 in positive line positive line of the differential pair of system clock inputs that drives input to the on- dimm clock driver. ck0 in negative line negative line of the differential pair of system clock inputs that drives the input to the on-dimm clock driver. ck1 in positive line terminated but not used on rdimms. ck1 in negative line terminated but not used on rdimms. cke[1:0] in active high cke high activates, and cke low deactivates internal clock signal s, and device input buffers and output drivers of the sdra ms. taking cke low provides precharge power-down and self refres h operation (all banks idle), or active power down (row active in any bank) s [3:0] in active low enables the command decoders for the asso ciated rank of sdram when low and dis- ables decoders when high. when decoders are disabled, new commands are ignored and previous operations continue. other combinations of these input signals perform unique functions, including disabling all outputs (except cke and odt) of the register(s) on the dimm or accessing internal control words in the register device(s). for modules with two registers, s[3:2] operate similarly to s[1:0] for the second set of register out- puts or register control words. odt[1:0] in active high on-die termination control signals r as , cas , we in active low when sampled at the positive rising edge of the clock, cas , ras , and we define the operation to be executed by the sdram. v refdq supply reference voltage for dq0-dq63 and cb0-cb7. v refca supply reference voltage for a0-a15, ba0-ba2, ras , cas , we , s0 , s1 , cke0, cke1, par_in, odt0 and odt1. ba[2:0] in ? selects which sdram bank of eight is activated. ba0 - ba2 define to which bank an active, read, write or precharge command is being applied. bank address also determines mode register is to be accessed during an mrs cycle. a[15:13, 12/bc ,11, 10/ap,[9:0] in ? provided the row address for active commands and the column address and auto precharge bit for read/write commands to select one location out of the mem- ory array in the respective bank. a10 is sampled during a precharge command to deter- mine whether the precharge applies to one bank (a10 low) or all banks (a10 high). if only one bank is to be precharged, the bank is selected by ba. a12 is also utilized for bl 4/8 identification for ??bl on the fly?? during cas command. the address inputs also pro- vide the op-code during mode register set commands. dq[63:0], cb[7:0] i/o ? data and check bi t input/output pins dm[8:0] in active high masks write data when high, issued concurrently with input data. v dd , v ss supply power and ground for the ddr sdram input buffers and core logic. v tt supply termination voltage for address/command/control/clock nets.
rev. 0.3 / jul. 2013 7 dqs[17:0] i/o positive edge positive line of the differential data strobe for input and output data. dqs[17:0] i/o negative edge negative line of the differential data strobe for input and output data. tdqs[17:9] tdqs[17:9] out tdqs/tdqs is applicable for x8 drams only. when enabled via mode register a11=1 in mr1,dram will enable the same termination resistance function on tdqs/tdqs that is applied to dqs/dqs . when disabled via mode regist er a11=0 in mr1, dm/tdqs will provide the data mask function and tdqs is not used. x4 drams must disable the tdqs function via mode register a11=0 in mr1 sa[2:0] in ? these signals are tied at the system planar to either v ss or v ddspd to configure the serial spd eeprom address range. sda i/o ? this bidirectional pin is used to transfer data into or out of the spd eeprom. a resistor must be connected from the sda bus line to v ddspd on the system pl anar to act as a pullup. scl in ? this signal is used to clock data into and out of the spd eeprom. a resistor may be con- nected from the scl bus time to v ddspd on the system planar to act as a pullup. event out (open drain) active low this signal indicates that a thermal event has been detected in the thermal sensing device.the system should guarantee the el ectrical level requirement is met for the event pin on ts/spd part. no pull-up resister is provided on dimm. v ddspd supply serial eeprom positive power supply wired to a separate power pin at the connector which supports from 3.0 volt to 3.6 volt (nominal 3.3v) operation. reset in the reset pin is connected to the reset pin on the register and to the reset pin on the dram. par_in in parity bit for the address and control bus. (?1 ?: odd, ?0 ?: even) err_out out (open drain) parity error detected on the address and cont rol bus. a resistor may be connected from err_out bus line to v dd on the system planar to act as a pull up. test used by memory bus analysis tools (unused (nc) on memory dimms) symbol type polarity function
rev. 0.3 / jul. 2013 8 pin assignments pin # front side (left 1?60) pin # back side (right 121?180) pin # front side (left 61?120) pin # back side (right 181?240) 1v ref dq 121 v ss 61 a2 181 a1 2 v ss 122 dq4 62 v dd 182 v dd 3 dq0 123 dq5 63 nc, ck1 183 v dd 4 dq1 124 v ss 64 nc, ck1 184 ck0 5 v ss 125 dm0,dqs9, tdqs9 65 v dd 185 ck0 6dqs0 126 nc,dqs9 , tdqs9 66 v dd 186 v dd 7 dqs0 127 v ss 67 v ref ca 187 event , nc 8 v ss 128 dq6 68 par_in, nc 188 a0 9 dq2 129 dq7 69 v dd 189 v dd 10 dq3 130 v ss 70 a10 / ap 190 ba1 11 v ss 131 dq12 71 ba0 191 v dd 12 dq8 132 dq13 72 v dd 192 ras 13 dq9 133 v ss 73 we 193 s0 14 v ss 134 dm1,dqs10, tdqs10 74 cas 194 v dd 15 dqs1 135 nc,dqs10 , tdqs10 75 v dd 195 odt0 16 dqs1 136 v ss 76 s1 , nc 196 a13 17 v ss 137 dq14 77 odt1, nc 197 v dd 18 dq10 138 dq15 78 v dd 198 s3 , nc 19 dq11 139 v ss 79 s2 , nc 199 v ss 20 v ss 140 dq20 80 v ss 200 dq36 21 dq16 141 dq21 81 dq32 201 dq37 22 dq17 142 v ss 82 dq33 202 v ss 23 v ss 143 dm2,dqs11, tdqs11 83 v ss 203 dm4,dqs13, tdqs13 24 dqs2 144 nc,dqs11 , tdqs11 84 dqs4 204 nc,dqs13 , tdqs13 25 dqs2 145 v ss 85 dqs4 205 v ss 26 v ss 146 dq22 86 v ss 206 dq38 27 dq18 147 dq23 87 dq34 207 dq39 28 dq19 148 v ss 88 dq35 208 v ss 29 v ss 149 dq28 89 v ss 209 dq44 30 dq24 150 dq29 90 dq40 210 dq45 31 dq25 151 v ss 91 dq41 211 v ss nc = no connect; rfu = reserved future use
rev. 0.3 / jul. 2013 9 32 v ss 152 dm3,dqs12, tdqs12 92 v ss 212 dm5,dqs14, tdqs14 33 dqs3 153 nc,dqs12 , tdqs12 93 dqs5 213 nc,dqs14 , tdqs14 34 dqs3 154 v ss 94 dqs5 214 v ss 35 v ss 155 dq30 95 v ss 215 dq46 36 dq26 156 dq31 96 dq42 216 dq47 37 dq27 157 v ss 97 dq43 217 v ss 38 v ss 158 cb4, nc 98 v ss 218 dq52 39 cb0, nc 159 cb5, nc 99 dq48 219 dq53 40 cb1, nc 160 v ss 100 dq49 220 v ss 41 v ss 161 nc,dm8,dqs17, tdqs17 101 v ss 221 dm6,dqs15, tdqs15 42 dqs8 162 nc,dqs17 , tdqs17 102 dqs6 222 nc,dqs15 , tdqs15 43 dqs8 163 v ss 103 dqs6 223 v ss 44 v ss 164 cb6, nc 104 v ss 224 dq54 45 cb2, nc 165 cb7, nc 105 dq50 225 dq55 46 cb3, nc 166 v ss 106 dq51 226 v ss 47 v ss 167 nc(test) 107 v ss 227 dq60 48 vtt, nc 168 reset 108 dq56 228 dq61 key key 109 dq57 229 v ss 49 vtt, nc 169 cke1, nc 110 v ss 230 dm7,dqs16, tdqs16 50 cke0 170 v dd 111 dqs7 231 nc,dqs16 , tdqs16 51 v dd 171 a15 112 dqs7 232 v ss 52 ba2 172 a14 113 v ss 233 dq62 53 err_out , nc 173 v dd 114 dq58 234 dq63 54 v dd 174 a12 / bc 115 dq59 235 v ss 55 a11 175 a9 116 v ss 236 v ddspd 56 a7 176 v dd 117 sa0 237 sa1 57 v dd 177 a8 118 scl 238 sda 58 a5 178 a6 119 sa2 239 v ss 59 a4 179 v dd 120 v tt 240 v tt 60 v dd 180 a3 pin # front side (left 1?60) pin # back side (right 121?180) pin # front side (left 61?120) pin # back side (right 181?240) nc = no connect; rfu = reserved future use
rev. 0.3 / jul. 2013 10 functional block diagram 32gb, 4gx72 module(4ra nk of x4) - page1 qcs2a qcs0a qodt0a qcke0a vdd qcs3a qcs1a qodt1a qcke1a vdd dqs dqs d0 dq [0:3] zq vss cs0 cs1 odt1 cke0 cke1 vdd dqs dqs d27 dq [0:3] zq vss cs0 cs1 odt0 odt1 cke0 cke1 vdd dqs dqs d1 dq [0:3] zq vss cs0 cs1 odt0 odt1 cke0 cke1 vdd dqs dqs d28 dq [0:3] zq vss cs0 cs1 odt0 odt1 cke0 cke1 vdd dqs dqs d2 dq [0:3] zq vss cs0 cs1 odt0 odt1 cke0 cke1 vdd dqs dqs d29 dq [0:3] zq vss cs0 cs1 odt0 odt1 cke0 cke1 vdd dqs dqs d3 dq [0:3] zq vss cs0 cs1 odt0 odt1 cke0 cke1 vdd dqs dqs d30 dq [0:3] zq vss cs0 cs1 odt0 odt1 cke0 cke1 vdd dqs dqs d4 dq [0:3 zq vss cs0 cs1 odt0 odt1 cke0 cke1 vdd dqs dqs d31 dq [0:3] zq vss cs0 cs1 odt0 odt1 cke0 cke1 vdd dqs dqs d5 dq [0:3] zq vss cs0 cs1 odt0 odt1 cke0 cke1 vdd dqs dqs d32 dq [0:3] zq vss cs0 cs1 odt0 odt1 cke0 cke1 vdd dqs dqs d6 dq [0:3] zq vss cs0 cs1 odt0 odt1 cke0 cke1 vdd dqs dqs d33 dq [0:3] zq vss cs0 cs1 odt0 odt1 cke0 cke1 vdd dqs dqs d7 dq [0:3] zq vss cs0 cs1 odt0 odt1 cke0 cke1 vdd dqs dqs d34 dq [0:3] zq vss cs0 cs1 odt0 odt1 cke0 cke1 vdd dqs dqs d8 dq [0:3 zq vss cs0 cs1 odt0 odt1 cke0 cke1 dqs dqs d35 dq [0:3] zq vss cs0 cs1 odt0 odt1 cke0 cke1 dqs3 dqs3 dq [24:27] memory buffer mdqs3 mdqs3 mdq [24:27] dqs12 dqs12 dq [28:31] mdqs12 mdqs12 mdq [28:31] dqs17 dqs17 cb [4:7] mdqs17 mdqs17 mcb [4:7] dqs2 dqs2 dq [16:19] mdqs2 mdqs2 mdq [16:19] dqs11 dqs11 dq [20:23] mdqs11 mdqs11 mdq [20:23] dqs9 dqs9 dq [4:7] mdqs9 mdqs9 mdq [4:7] dqs0 dqs0 dq [0:3] mdqs0 mdqs0 mdq [0:3] dqs10 dqs10 dq [12:15] mdqs10 mdqs10 mdq [12:15] dqs1 dqs1 dq [8:11] mdqs1 mdqs1 mdq [8:11] odt0 notes: 1. unless otherwise noted, resistor values are 10 ohms
qcs2b qcs0b qodt0b qcke0b vdd qcs3b qcs1b qodt1b qcke1b vdd dqs dqs d9 dq [0:3] zq vss cs0 cs1 odt1 cke0 cke1 vdd dqs dqs d18 dq [0:3] zq vss cs0 cs1 odt0 odt1 cke0 cke1 vdd dqs dqs d10 dq [0:3] zq vss cs0 cs1 odt0 odt1 cke0 cke1 vdd dqs dqs d19 dq [0:3] zq vss cs0 cs1 odt0 odt1 cke0 cke1 vdd dqs dqs d2=11 dq [0:3] zq vss cs0 cs1 odt0 odt1 cke0 cke1 vdd dqs dqs d20 dq [0:3] zq vss cs0 cs1 odt0 odt1 cke0 cke1 vdd dqs dqs d12 dq [0:3] zq vss cs0 cs1 odt0 odt1 cke0 cke1 vdd dqs dqs d21 dq [0:3] zq vss cs0 cs1 odt0 odt1 cke0 cke1 vdd dqs dqs d13 dq [0:3 zq vss cs0 cs1 odt0 odt1 cke0 cke1 vdd dqs dqs d22 dq [0:3] zq vss cs0 cs1 odt0 odt1 cke0 cke1 vdd dqs dqs d14 dq [0:3] zq vss cs0 cs1 odt0 odt1 cke0 cke1 vdd dqs dqs d23 dq [0:3] zq vss cs0 cs1 odt0 odt1 cke0 cke1 vdd dqs dqs d15 dq [0:3] zq vss cs0 cs1 odt0 odt1 cke0 cke1 vdd dqs dqs d24 dq [0:3] zq vss cs0 cs1 odt0 odt1 cke0 cke1 vdd dqs dqs d16 dq [0:3] zq vss cs0 cs1 odt0 odt1 cke0 cke1 vdd dqs dqs d25 dq [0:3] zq vss cs0 cs1 odt0 odt1 cke0 cke1 vdd dqs dqs d17 dq [0:3 zq vss cs0 cs1 odt0 odt1 cke0 cke1 dqs dqs d26 dq [0:3] zq vss cs0 cs1 odt0 odt1 cke0 cke1 mdqs3 mdqs3 dq [32:35] memory buffer mdqs4 mdqs4 mdq [32:35] mdqs13 mdqs13 dq [36:39] mdqs13 mdqs13 mdq [36:39] mdqs8 mdqs8 mcb [0:3] mdqs8 mdqs8 mcb [0:3] dqs5 dqs5 dq [40:43] mdqs5 mdqs5 mdq [40:43] dqs14 dqs14 dq [44:47] mdqs14 mdqs14 mdq [44:47] dqs15 dqs15 dq [52:55] mdqs15 mdqs15 mdq [52:55] dqs6 dqs6 dq [48:51] mdqs6 mdqs6 mdq [48:51] dqs16 dqs16 dq [60:63] mdqs16 mdqs16 mdq [60:63] dqs7 dqs7 dq [56:59] mdqs7 mdqs7 mdq [56:59] odt0 a0 serial pd w/ stand alone thermal sensor a1 sa0 sa1 sda scl event sa2 a2 d0?d35 v dd v tt v ddspd d0?d35 vrefdq spd vrefca v ss d0?d35 d0?d35 event rev. 0.3 / jul. 2013 11 32gb, 4gx72 module(4ra nk of x4) - page2
ck1 ck1 cs[3:0] ba[2:0] ras cas we cke[3:0] ck0 ck0 par_in cs2a ? cs0 : sdrams d[8:0] cs3a ? cs0 : sdrams d[35:27] err_out reset qreset : all sdrams m e m o r y b u f f odt[1:0] e r 1. ck0 and ck0 are terminated with 120 ohms 5% resistor. 2. ck1 and ck1 are terminated with 120 ohms 5% resistor, but is not used. 3. unless othersiwe noted resistors are 22 ohms 5% cs0a ? cs1 : sdrams d[8:0] cs1a ? cs1 : sdrams d[35:27] cs2b ? cs0 : sdrams d[17:9] cs3b ? cs0 : sdrams d[26:18] cs0b ? cs1 : sdrams d[17:9] cs1b ? cs1 : sdrams d[26:18] ba[2:0]a ? ba[2:0]: sdrams d[8:0], d[35:27] ba[2:0]b ? ba[2:0]: sdrams d[26:9] a[15:0]a ? a[15:0]: sdrams d[8:0], d[35:27] a[15:0]b ? a[15:0]: sdrams d[26:9] a[15:0] rasa ? ras : sdrams d[8:0], d[35:27] rasb ? ras : sdrams d[26:9] casa ? cas : sdrams d[8:0], d[35:27] casb ? cas : sdrams d[26:9] wea ? we : sdrams d[8:0], d[35:27] web ? we : sdrams d[26:9] cke2a ? cke0 : d[8:0] cke0a ? cke1 : d[8:0] cke3a ? cke0 : d[26:18] cke1a ? cke1 : d[26:18] cke2b ? cke0 : d[17:9] cke0b ? cke1 : d[17:9] cke3b ? cke0 : d[35:27] cke1b ? cke1 : d[35:27] odt0a ? odt1: sdrams d[8:0] odt1a ? odt1: sdrams d[35:27] odt0b ? odt1: sdrams d[17:9] odt1b ? odt1: sdrams d[26:18] ck0 ? ck: sdrams d[8:0] ck1 ? ck: sdrams d[35:27] ck2 ? ck: sdrams d[17:9] ck3 ? ck: sdrams d[26:18] ck 0 ? ck : sdrams d[8:0] ck 1 ? ck : sdrams d[35:27] ck 2 ? ck : sdrams d[17:9] ck 3 ? ck : sdrams d[26:18] rev. 0.3 / jul. 2013 12 32gb, 4gx72 module(4ra nk of x4) - page3
rev. 0.3 / jul. 2013 13 absolute maximum ratings absolute maximum dc ratings notes: 1. stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operat ion of the device at these or any other conditions above those indicated in the operational sections of this specif ication is not implied. exposure to absolute maximum rat - ing conditions for extended pe riods may affect reliability. 2. storage temperature is the case surface temperature on the center/top side of the dram. for the measurement conditions, please refer to jesd51-2 standard. 3. vdd and vddq must be within 300mv of each other at all times; and vref must not be greater than 0.6xvddq,when vdd and vddq are less than 500mv; vref may be equal to or less than 300mv. ? dram component operat ing temperature range notes: 1. operating temperature toper is the case surface temperature on the center / top side of the dram. for mea - surement conditions, please refer to the jedec document jesd51-2. 2. the normal temperature range specifies the temperatures where all dram specificatio ns will be supported. dur - ing operation, the dram case temperature must be maintained between 0 - 85 o c under all operating conditions. 3. some applications require operation of the dr am in the extended temperature range between 85 o c and 95 o c case temperature. full specifications are guaranteed in this range, but the following additional conditions apply: a. refresh commands must be doubled in frequency, theref ore reducing the refresh interval trefi to 3.9 s. it is also possible to specify a component with 1x refres h (trefi to 7.8s) in the extended temperature range. please refer to the dimm spd for option availability b. if self-refresh operation is required in the extended temperature range, then it is mandatory to use the manual self-refresh mode with extended temperature range capability (mr2 a6 = 0b and mr2 a7 = 1b). ddr3 sdrams support extended temperature range an d please refer to compon ent datasheet and/or the dimm spd for trefi requirements in the extended temperature range absolute maximum dc ratings symbol parameter rating units notes vdd voltage on vdd pin relative to vss - 0.4 v ~ 1.80 v v 1,3 vddq voltage on vddq pin relative to vss - 0.4 v ~ 1.80 v v 1,3 v in , v out voltage on any pin relative to vss - 0.4 v ~ 1.80 v v 1 t stg storage temperature -55 to +100 o c1, 2 temperature range symbol parameter rating units notes t oper normal operating temperature range 0 to 85 o c 1,2 extended temperature range 85 to 95 o c1,3
symbol parameter rating units notes min. typ. max. supply voltage supply voltage for output 1. if minimum limit is exceeded, input levels sh all be governed by ddr3l specifications. 2. under 1.5v operation, this ddr3l device operates to the ddr3 specifications under the same speed timings as defined for this device. 3. once initialized for ddr3 operation, ddr3l operation may only b e used if the device is in reset while vdd and vddq are changed for ddr3l operation (see figure 0). rev. 0.3 / jul. 2013 14 ac & dc operating conditions recommended dc operating conditions recommended dc operating conditions - ddr3l (1.35v) operation symbol parameter rating units notes min. typ. max. vdd supply voltage 1.283 1.35 1.45 v 1,2,3,4 vddq supply voltage for output 1.283 1.35 1.45 v 1,2,3,4 notes: 1. maximum dc value may not be greater than 1.425v. the dc value is the linear average of vdd/vddq (t) over a very long period of time (e.g., 1 sec). 2. if maximum limit is exceeded, input levels shall be governed by ddr3 specifications. 3. under these supply voltages, the device operates to this ddr3l specification. 4. once initialized for ddr3l operation, ddr3 operation may only be used if the device is in reset while vdd and vddq are changed for ddr3 operation (see figure 0). recommended dc operating conditio ns - - ddr3 (1.5v) operation vdd 1.425 1.5 1.575 v 1,2,3 vd dq 1.425 1.5 1.575 v 1,2,3 no tes:
rev. 0.3 / jul. 2013 15 figure 0 - vdd/vddq voltage switch between ddr3l and ddr3 note 1: from time point
rev. 0.3 / jul. 2013 16 standard speed bins ddr3 sdram standard speed bins include tck, trcd , trp, tras and trc for each corresponding bin. ddr3-800 speed bins for specific notes see "speed bin table notes" on page 21. speed bin ddr3-800e unit notes cl - nrcd - nrp 6-6-6 parameter symbol min max internal read command to first data t aa 15 20 ns act to internal read or write delay time t rcd 15 ? ns pre command period t rp 15 ? ns act to act or ref command period t rc 52.5 ? ns act to pre command period t ras 37.5 9 * trefi ns cl = 6 cwl = 5 t ck(avg) 2.5 3.3 ns 1,2,3 supported cl settings 6 n ck supported cwl settings 5 n ck
rev. 0.3 / jul. 2013 17 ddr3-1066 speed bins for specific notes see "speed bin table notes" on page 21. speed bin ddr3-1066f unit note cl - nrcd - nrp 7-7-7 parameter symbol min max internal read command to first data t aa 13.125 20 ns act to internal read or write delay time t rcd 13.125 ? ns pre command period t rp 13.125 ? ns act to act or ref command period t rc 50.625 ? ns act to pre command period t ras 37.5 9 * trefi ns cl = 6 cwl = 5 t ck(avg) 2.5 3.3 ns 1,2,3,6 cwl = 6 t ck(avg) reserved ns 1,2,3,4 cl = 7 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1,2,3,4 cl = 8 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1,2,3 supported cl settings 6, 7, 8 n ck supported cwl settings 5, 6 n ck
rev. 0.3 / jul. 2013 18 ddr3-1333 speed bins for specific notes see "speed bin table notes" on page 21. speed bin ddr3-1333h unit note cl - nrcd - nrp 9-9-9 parameter symbol min max internal read command to first data t aa 13.5 (13.125) 5,10 20 ns act to internal read or write delay time t rcd 13.5 (13.125) 5,10 ?ns pre command period t rp 13.5 (13.125) 5,10 ?ns act to act or ref command period t rc 49.5 (49.125) 5,10 ?ns act to pre command period t ras 36 9 * trefi ns cl = 6 cwl = 5 t ck(avg) 2.5 3.3 ns 1,2,3,7 cwl = 6 t ck(avg) reserved ns 1,2,3,4,7 cwl = 7 t ck(avg) reserved ns 4 cl = 7 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1,2,3,4,7 (optional) 5,10 cwl = 7 t ck(avg) reserved ns 1,2,3,4 cl = 8 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1,2,3,7 cwl = 7 t ck(avg) reserved ns 1,2,3,4 cl = 9 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 ns 1,2,3,4 cl = 10 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 ns 1,2,3 (optional) ns 5 supported cl settings 6, 7, 8, 9, 10 n ck supported cwl settings 5, 6, 7 n ck
rev. 0.3 / jul. 2013 19 ddr3-1600 speed bins for specific notes see "speed bin table notes" on page 21. speed bin ddr3-1600k unit note cl - nrcd - nrp 11-11-11 parameter symbol min max internal read command to first data t aa 13.75 (13.125) 5,10 20 ns act to internal read or write delay time t rcd 13.75 (13.125) 5,10 ?ns pre command period t rp 13.75 (13.125) 5,10 ?ns act to act or ref command period t rc 48.75 (48.125) 5,10 ?ns act to pre command period t ras 35 9 * trefi ns cl = 6 cwl = 5 t ck(avg) 2.5 3.3 ns 1,2,3,8 cwl = 6 t ck(avg) reserved ns 1,2,3,4,8 cwl = 7 t ck(avg) reserved ns 4 cl = 7 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1,2,3,4,8 (optional) 5,10 cwl = 7 t ck(avg) reserved ns 1,2,3,4,8 cwl = 8 t ck(avg) reserved ns 4 cl = 8 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1,2,3,8 cwl = 7 t ck(avg) reserved ns 1,2,3,4,8 cwl = 8 t ck(avg) reserved ns 1,2,3,4 cl = 9 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 ns 1,2,3,4,8 (optional) 5,10 cwl = 8 t ck(avg) reserved ns 1,2,3,4 cl = 10 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 ns 1,2,3,8 cwl = 8 t ck(avg) reserved ns 1,2,3,4 cl = 11 cwl = 5, 6,7 t ck(avg) reserved ns 4 cwl = 8 t ck(avg) 1.25 <1.5 ns 1,2,3 supported cl settings 5, 6, 7, 8, 9, 10, 11 n ck supported cwl settings 5, 6, 7, 8 n ck
rev. 0.3 / jul. 2013 20 ddr3-1866 speed bins for specific notes see "speed bin table notes" on page 21. speed bin ddr3-1866m unit note cl - nrcd - nrp 13-13-13 parameter symbol min max internal read command to first data t aa 13.91 (13.125) 5,11 20 ns act to internal read or write delay time t rcd 13.91 (13.125) 5,11 ?ns pre command period t rp 13.91 (13.125) 5,11 ?ns act to pre command period t ras 34 9 * trefi ns act to act or pre command period t rc 47.91 (47.125) 5,11 -ns cl = 6 cwl = 5 t ck(avg) 2.5 3.3 ns 1,2,3,9 cwl = 6 t ck(avg) reserved ns 1,2,3,4,9 cwl = 7,8,9 t ck(avg) reserved ns 4 cl = 7 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1,2,3,4,9 cwl = 7,8,9 t ck(avg) reserved ns 4 cl = 8 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1,2,3,9 cwl = 7 t ck(avg) reserved ns 1,2,3,4,9 cwl = 8,9 t ck(avg) reserved ns 4 cl = 9 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 ns 1,2,3,4,9 cwl = 8 t ck(avg) reserved ns 1,2,3,4,9 cwl = 9 t ck(avg) reserved ns 4 cl = 10 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 ns 1,2,3,9 cwl = 8 t ck(avg) reserved ns 1,2,3,4,9 cl = 11 cwl = 5,6,7 t ck(avg) reserved ns 4 cwl = 8 t ck(avg) 1.25 <1.5 ns 1,2,3,4,9 cwl = 9 t ck(avg) reserved ns 1,2,3,4 cl = 12 cwl = 5,6,7,8 t ck(avg) reserved ns 4 cwl = 9 t ck(avg) reserved ns 1,2,3,4 cl = 13 cwl = 5,6,7,8 t ck(avg) reserved ns 4 cwl = 9 t ck(avg) 1.07 <1.25 ns 1, 2, 3 supported cl settings 6, 7, 8, 9, 10, 11, 13 n ck supported cwl settings 5, 6, 7, 8, 9 n ck
rev. 0.3 / jul. 2013 21 speed bin table notes absolute specification (t oper ; v ddq = v dd = 1.35v +1.000/- 0.067 v); (t oper ; v ddq = v dd = 1.5v +/- 0.075 v); 1. the cl setting and cwl setting result in tck(avg).min and tck(avg).max requirements. when mak - ing a selection of tck(avg), both need to be fulfille d: requirements from cl setting as well as require - ments from cwl setting. 2. tck(avg).min limits: since cas latency is not pure ly analog - data and strobe output are synchro - nized by the dll - all possible intermediate freque ncies may not be guaranteed. an application should use the next smaller jedec standard tck(avg) valu e (3.0, 2.5, 1.875, 1.5, or 1.25 ns) when calculat - ing cl [nck] = taa [ns] / tck(avg) [ns], rounding up to the next ?supported cl?, where tck(avg) = 3.0 ns should only be used for cl = 5 calculation. 3. tck(avg).max limits: calculate tck(avg) = taa.ma x / cl selected and round the resulting tck(avg) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). this result is tck(avg).max corresponding to cl selected. 4. ?reserved? settings are not allowed. user must program a different value. 5. ?optional? settings allow certain devices in the indust ry to support this setting, however, it is not a man - datory feature. refer to dimm data sheet and/or th e dimm spd information if and how this setting is supported. 6. any ddr3-1066 speed bin also supports functional op eration at lower frequencies as shown in the table which are not subject to production te sts but verified by de sign/characterization. 7. any ddr3-1333 speed bin also supports functional op eration at lower frequencies as shown in the table which are not subject to production te sts but verified by de sign/characterization. 8. any ddr3-1600 speed bin also supports functional op eration at lower frequencies as shown in the table which are not subject to production test s but verified by desi gn/characterization. 9. any ddr3-1866 speed bin also supports functional op eration at lower frequencies as shown in the table which are not subject to production te sts but verified by de sign/characterization. 10. ddr3 sdram devices supporting optional down binni ng to cl=7 and cl=9, and taa/trcd/trp must be 13.125 ns or lower. spd settings must be programmed to match. for example, ddr3-1333h devices supporting down binning to ddr3-1066f shou ld program 13.125 ns in spd bytes for taamin (byte 16), trcdmin (byte 18), and trpmin (byte 20) . ddr3-1600k devices supporting down binning to ddr3-1333h or ddr3-1600f should program 13.125 ns in spd bytes for taamin (byte 16), trcdmin (byte 18), and trpmin (byte 20). once trp (byte 20) is programmed to 13.125ns, trcmin (byte 21,23) also should be programmed accordingly. for ex ample, 49.125ns (trasmin + trpmin = 36 ns + 13.125 ns) for ddr3-1333h and 48.125ns (trasmin + trpmin = 35 ns + 13.125 ns) for ddr3-1600k. 11. ddr3 sdram devices supporting opti onal down binning to cl=11, cl=9 and cl=7, taa/trcd/trpmin must be 13.125ns. spd setting must be programe d to match. for example, ddr3-1866 devices sup - porting down binning to ddr3-1600 or ddr3-1333 or 1066 should program 13.125ns in spd bytes for taamin(byte 16), trcdmin(byte 18) and trpmin(byte 20) is programmed to 13.125ns, trcmin(byte 21,23) also should be programmed accordingly. fo r example, 47.125ns (trasmin + trpmin = 34ns + 13.125ns)
rev. 0.3 / jul. 2013 22 idd and iddq specification pa rameters and test conditions idd and iddq measurement conditions in this chapter, idd and iddq measurement conditions such as test load and patt erns are defined. figure 1. shows the setup and test load for idd and iddq measurements. ? idd currents (such as idd0, idd1, idd2n, idd2nt , idd2p0, idd2p1, idd2q, idd3n, idd3p, idd4r, idd4w, idd5b, idd6, idd6et and idd7) are measured as time-averaged currents with all vdd balls of the ddr3 sdram under test tied together. any iddq current is not included in idd currents. ? iddq currents (such as iddq2nt and iddq4r) are measured as time-averaged currents with all vddq balls of the ddr3 sdram under test tied toge ther. any idd current is not included in iddq cur - rents. ? ? ? ? ? ?
rev. 0.3 / jul. 2013 23 figure 1 - measurement setup and test load for idd and iddq (optional) measurements [note: dimm level output test load condition may be different from above figure 2 - correlation from simulated channel io power to actual ch annel io power supported by iddq measurement v dd ddr3(l) sdram v ddq reset ck/ck dqs, dqs cs ras , cas , we a, ba odt zq v ss v ssq dq, dm, tdqs, tdqs cke r tt = 25 ohm v ddq /2 i dd i ddq (optional) application specific memory channel environment channel io power simulation iddq simulation iddq simulation channel io power number iddq test load correction
rev. 0.3 / jul. 2013 24 table 1 -timings used for idd an d iddq measurement-loop patterns table 2 -basic idd and id dq measurement conditions symbol ddr3-1066 ddr3-1333 ddr3-1600 ddr3-1866 unit 7-7-7 9-9-9 11-11-11 13-13-13 t ck 1.875 1.5 1.25 1.25 ns cl 7 9 11 11 nck n rcd 7 9 11 11 nck n rc 27 33 39 39 nck n ras 20 24 28 28 nck n rp 7 9 11 11 nck n faw 1kb page size 20 20 24 24 nck 2kb page size 27 30 32 32 nck n rrd 1kb page size 4 4 5 5 nck 2kb page size 6 5 6 6 nck n rfc -512mb 48 60 72 72 nck n rfc -1 gb 59 74 88 88 nck n rfc - 2 gb 86 107 128 128 nck n rfc - 4 gb 139 174 208 208 nck n rfc - 8 gb 187 234 280 280 nck symbol description i dd0 operating one bank active-precharge current ? i dd1 operating one bank active-precharge current cke: high; external clock: on; tck, n rc, nras, nrcd, cl: see table 1; bl: 8 a) ; al: 0; cs : high between act, rd and pre; command, address; bank address inputs, da ta io: partially toggling ac cording to table 4; dm: stable at 0; bank activity: cycling with on bank active at a time: 0,0,1,1,2,2,... (see table 4); output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 4.
rev. 0.3 / jul. 2013 25 i dd2n precharge standby current cke: high; external clock: on ; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: partially toggling accord ing to table 5; data io: mid_level; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 5. i dd2nt precharge standby odt current cke: high; external clock: on ; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: partially toggling accord ing to table 6; data io: mid_level; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers b) ; odt signal: toggling according to table 6; pattern details: see table 6. i dd2p0 precharge power-down current slow exit cke: low; external clock: on; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: mid_level; dm: st able at 0; bank activity: all banks closed; output buf- fer and rtt: enabled in mode registers b) ; odt signal: stable at 0; prec harge power down mode: slow exit c) i dd2p1 precharge power-down current fast exit cke: low; external clock: on; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: mid_level; dm: st able at 0; bank activity: all banks closed; output buf- fer and rtt: enabled in mode registers b) ; odt signal: stable at 0; prec harge power down mode: fast exit c) i dd2q precharge quiet standby current cke: high; external clock: on ; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: mid_level; dm: st able at 0; bank activity: all banks closed; output buf- fer and rtt: enabled in mode registers b) ; odt signal: stable at 0 i dd3n active standby current cke: high; external clock: on ; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: partially toggling accord ing to table 5; data io: mid_level; dm: stable at 0; bank activity: all banks open; output buffer and rt t: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 5. i dd3p active power-down current cke: low; external clock: on; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: mid_level; dm: st able at 0; bank activity: all banks open; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0 symbol description
rev. 0.3 / jul. 2013 26 i dd4r operating burst read current cke: high; external clock: on ; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : high between rd; command, address, bank address inputs: partially toggling according to tabl e 7; data io: seamless read data burst with different data between one burst and the next one according to tabl e 7; dm: stable at 0; bank activity: all banks open, rd commands cycling through banks: 0,0,1,1,2,2,...(see table 7); output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 7. i dd4w operating burst write current cke: high; external clock: on ; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : high between wr; command, address, bank address inputs: partially toggling according to tabl e 8; data io: seamless read data burst with different data between one burst and the next one according to tabl e 8; dm: stable at 0; bank activity: all banks open, wr commands cycling through banks: 0,0,1,1,2,2,...(see table 8); output buffer and rtt: enabled in mode registers b) ; odt signal: stable at high ; pattern details: see table 8. i dd5b burst refresh current cke: high; external clock: on; tck, cl, nrfc: see table 1; bl: 8 a) ; al: 0; cs : high between ref; command, address, bank address inputs: partiall y toggling according to table 9; data io: mid_level; dm: stable at 0; bank activity: ref command every nref (see table 9); output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 9. i dd6 self-refresh current: normal temperature range t case : 0 - 85 o c; auto self-refresh (asr): disabled d) ;self-refresh temperature range (srt): normal e) ; cke: low; external clock: off; ck and ck : low; cl: see table 1; bl: 8 a) ; al: 0; cs , command, address, bank address inputs, data io: mid_level; dm: stable at 0; bank activity: self-refresh operation; output buffer and rtt: enabled in mode registers b) ; odt signal: mid_level i dd6et self-refresh current: extended temperature range (optional) t case : 0 - 95 o c; auto self-refresh (asr): disabled d) ;self-refresh temperature range (srt): extended e) ; cke: low; external clock: off; ck and ck : low; cl: see table 1; bl: 8 a) ; al: 0; cs , command, address, bank address inputs, data io: mid_level; dm: stable at 0; bank activity: extended temperature self-refresh operation; output buffer and rtt: enabled in mode registers b) ; odt signal: mid_level symbol description
rev. 0.3 / jul. 2013 27 a) burst length: bl8 fixed by mrs: set mr0 a[1,0]=00b b) output buffer enable: set mr1 a[12] = 0b; set mr1 a[ 5,1] = 01b; rtt_nom enable: set mr1 a[9,6,2] = 011b; rtt_wr enable: set mr2 a[10,9] = 10b c) precharge power down mode: set mr0 a12=0b for slow exit or mr0 a12 = 1b for fast exit d) auto self-refresh (asr): set mr2 a6 = 0b to disable e) self-refresh temperature range (srt): set mr2 a7 = 0b for normal or 1b for extended temperature range f) read burst type: nibble sequential, set mr0 a[3] = 0b i dd7 operating bank interleave read current cke: high; external clock: on; tck, nrc, nr as, nrcd, nrrd, nfaw, cl: see table 1; bl: 8 a),f) ; al: cl-1; cs : high between act and rda; command, address, bank a ddress inputs: partially togg ling according to table 10; data io: read data burst with different data betw een one burst and the next one according to table 10; dm: stable at 0; bank activity: two times interleaved cycling through banks (0, 1,.. .7) with different address- ing, wee table 10; output buffer an d rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 10. symbol description
rev. 0.3 / jul. 2013 28 table 3 - idd0 measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are mid-level. b) dq signals are mid-level. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 act 0 0 1 1 0 0 00 0 0 0 0 - 1,2 d, d 1 0 0 0 0 0 00 0 0 0 0 - 3,4 d , d 1111 0 0000 0 0 0 - ... repeat pattern 1...4 until nras - 1, truncate if necessary nras pre 0 0 1 0 0 0 00 0 0 0 0 - ... repeat pattern 1...4 until n rc - 1, truncate if necessary 1*nrc+0 act 0 0 1 1 0 0 00 0 0 f 0 - 1*nrc+1, 2 d, d 1 0 0 0 0 0 00 0 0 f 0 - 1*nrc+3, 4 d , d 1111 0 0000 0 f 0 - ... repeat pattern 1...4 until 1*nrc + nras - 1, truncate if necessary 1*nrc+nras pre 0 0 1 0 0 0 00 0 0 f 0 - ... repeat pattern 1...4 until 2*nrc - 1, truncate if necessary 1 2*nrc repeat sub-loop 0, use ba[2:0] = 1 instead 2 4*nrc repeat sub-loop 0, use ba[2:0] = 2 instead 3 6*nrc repeat sub-loop 0, use ba[2:0] = 3 instead 4 8*nrc repeat sub-loop 0, use ba[2:0] = 4 instead 5 10*nrc repeat sub-loop 0, use ba[2:0] = 5 instead 6 12*nrc repeat sub-loop 0, use ba[2:0] = 6 instead 7 14*nrc repeat sub-loop 0, use ba[2:0] = 7 instead
rev. 0.3 / jul. 2013 29 table 4 - idd1 measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are used according to rd commands, otherwise mid-level. b) burst sequence driven on each dq signal by read co mmand. outside burst operation, dq signals are mid_level. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 act001100000000 - 1,2 d, d 1 0 0 0 0 0 00 0 0 0 0 - 3,4 d , d 111100000000 - ... repeat pattern 1...4 until nrcd - 1, truncate if necessary nrcd rd 0 1 0 1 0 0 00 0 0 0 0 00000000 ... repeat pattern 1...4 until nras - 1, truncate if necessary nras pre001000000000 - ... repeat pattern 1...4 until nr c - 1, truncate if necessary 1*nrc+0 act 0 0 1 1 0 0 00 0 0 f 0 - 1*nrc+1,2 d, d 1 0 0 0 0 0 00 0 0 f 0 - 1*nrc+3,4 d , d 1111000000f0 - ... repeat pattern nrc + 1,. ..4 until nrc + nrce - 1, truncate if necessary 1*nrc+nrcd rd 0 1 0 1 0 0 00 0 0 f 0 00110011 ... repeat pattern nrc + 1, ...4 until nrc + nras - 1, truncate if necessary 1*nrc+nras pre 0 0 1 0 0 0 00 0 0 f 0 - ... repeat pattern nrc + 1, ...4 until *2 nrc - 1, truncate if necessary 1 2*nrc repeat sub-loop 0, use ba[2:0] = 1 instead 2 4*nrc repeat sub-loop 0, use ba[2:0] = 2 instead 3 6*nrc repeat sub-loop 0, use ba[2:0] = 3 instead 4 8*nrc repeat sub-loop 0, use ba[2:0] = 4 instead 5 10*nrc repeat sub-loop 0, use ba[2:0] = 5 instead 6 12*nrc repeat sub-loop 0, use ba[2:0] = 6 instead 7 14*nrc repeat sub-loop 0, use ba[2:0] = 7 instead
rev. 0.3 / jul. 2013 30 table 5 - idd2n and idd3n measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are mid-level. b) dq signals are mid-level. table 6 - idd2nt and iddq2n t measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are mid-level. b) dq signals are mid-level. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 d10000000000 - 1d10000000000- 2d 111 1 0 0 0 0 0 f 0 - 3d 111 1 0 0 0 0 0 f 0 - 1 4-7 repeat sub-loop 0, use ba[2:0] = 1 instead 2 8-11 repeat sub-loop 0, use ba[2:0] = 2 instead 3 12-15 repeat sub-loop 0, use ba[2:0] = 3 instead 4 16-19 repeat sub-loop 0, use ba[2:0] = 4 instead 5 20-23 repeat sub-loop 0, use ba[2:0] = 5 instead 6 24-17 repeat sub-loop 0, use ba[2:0] = 6 instead 7 28-31 repeat sub-loop 0, use ba[2:0] = 7 instead ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 d10000000000 - 1d10000000000- 2d 1111 0 0 0 0 0 f 0 - 3d 1111 0 0 0 0 0 f 0 - 1 4-7 repeat sub-loop 0, but odt = 0 and ba[2:0] = 1 2 8-11 repeat sub-loop 0, but odt = 1 and ba[2:0] = 2 3 12-15 repeat sub-loop 0, but odt = 1 and ba[2:0] = 3 4 16-19 repeat sub-loop 0, but odt = 0 and ba[2:0] = 4 5 20-23 repeat sub-loop 0, but odt = 0 and ba[2:0] = 5 6 24-17 repeat sub-loop 0, but odt = 1 and ba[2:0] = 6 7 28-31 repeat sub-loop 0, but odt = 1 and ba[2:0] = 7
rev. 0.3 / jul. 2013 31 table 7 - idd4r and iddq4r measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are used according to rd commands, otherwise mid-level. b) burst sequence driven on each dq signal by read co mmand. outside burst operation, dq signals are mid-level. table 8 - idd4w measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are used according to wr commands, otherwise mid-level. b) burst sequence driven on each dq signal by write co mmand. outside burst operation, dq signals are mid-level. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 rd 0 1 0 1 0 0 00 0 0 0 0 00000000 1d100000000000- 2,3 d ,d 1111 0 0000 0 0 0 - 4 rd 0 1 0 1 0 0 00 0 0 f 0 00110011 5d1000000000f0- 6,7 d ,d 1111 0 0000 0 f 0 - 1 8-15 repeat sub-loop 0, but ba[2:0] = 1 2 16-23 repeat sub-loop 0, but ba[2:0] = 2 3 24-31 repeat sub-loop 0, but ba[2:0] = 3 4 32-39 repeat sub-loop 0, but ba[2:0] = 4 5 40-47 repeat sub-loop 0, but ba[2:0] = 5 6 48-55 repeat sub-loop 0, but ba[2:0] = 6 7 56-63 repeat sub-loop 0, but ba[2:0] = 7 ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 wr 0 1 0 0 1 0 00 0 0 0 0 00000000 1d100010000000- 2,3 d ,d 1111 1 0000 0 0 0 - 4 wr 0 1 0 0 1 0 00 0 0 f 0 00110011 5d1000100000f0- 6,7 d ,d 1111 1 0000 0 f 0 - 1 8-15 repeat sub-loop 0, but ba[2:0] = 1 2 16-23 repeat sub-loop 0, but ba[2:0] = 2 3 24-31 repeat sub-loop 0, but ba[2:0] = 3 4 32-39 repeat sub-loop 0, but ba[2:0] = 4 5 40-47 repeat sub-loop 0, but ba[2:0] = 5 6 48-55 repeat sub-loop 0, but ba[2:0] = 6 7 56-63 repeat sub-loop 0, but ba[2:0] = 7
rev. 0.3 / jul. 2013 32 table 9 - idd5b measur ement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are mid-level. b) dq signals are mid-level. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 ref 0 0 0 1 0 0 0 0 0 0 0 - 11.2 d, d 1 0 0 0 0 0 00 0 0 0 0 - 3,4 d , d 1111 0 0000 0 f 0 - 5...8 repeat cycles 1...4, but ba[2:0] = 1 9...12 repeat cycles 1...4, but ba[2:0] = 2 13...16 repeat cycles 1...4, but ba[2:0] = 3 17...20 repeat cycles 1...4, but ba[2:0] = 4 21...24 repeat cycles 1...4, but ba[2:0] = 5 25...28 repeat cycles 1...4, but ba[2:0] = 6 29...32 repeat cycles 1...4, but ba[2:0] = 7 2 33...nrfc-1 repeat sub-loop 1, until nrfc - 1. truncate, if necessary.
rev. 0.3 / jul. 2013 33 table 10 - idd7 meas urement-loop pattern a) attention! sub-loops 10-19 have inverse a[6:3] pattern and data pattern than sub-loops 0-9 ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 act 0 0 1 1 0 0 00 0 0 0 0 - 1 rda 0 1 0 1 0 0 00 1 0 0 0 00000000 2 d 1 0 0 0 0 0 00 0 0 0 0 - ... repeat above d command until nrrd - 1 1 nrrd act 0 0 1 1 0 1 00 0 0 f 0 - nrrd+1 rda 0 1 0 1 0 1 00 1 0 f 0 00110011 nrrd+2 d 1 0 0 0 0 1 00 0 0 f 0 - ... repeat above d command until 2* nrrd - 1 2 2*nrrd repeat sub-loop 0, but ba[2:0] = 2 3 3*nrrd repeat sub-loop 1, but ba[2:0] = 3 4 4*nrrd d 1 0 0 0 0 3 00 0 0 f 0 - assert and repeat abov e d comman d until nfaw - 1, if necessary 5 nfaw repeat sub-loop 0, but ba[2:0] = 4 6 nfaw+nrrd repeat sub-loop 1, but ba[2:0] = 5 7 nfaw+2*nrrd repeat sub-loop 0, but ba[2:0] = 6 8 nfaw+3*nrrd repeat sub-loop 1, but ba[2:0] = 7 9 nfaw+4*nrrd d 1 0 0 0 0 7 00 0 0 f 0 - assert and repeat abov e d command until 2* nfaw - 1, if necessary 10 2*nfaw+0 act 0 0 1 1 0 0 00 0 0 f 0 - 2*nfaw+1 rda 0 1 0 1 0 0 00 1 0 f 0 00110011 2&nfaw+2 d 1 0 0 0 0 0 00 0 0 f 0 - repeat above d command until 2* nfaw + nrrd - 1 11 2*nfaw+nrrd act 0 0 1 1 0 1 00 0 0 0 0 - 2*nfaw+nrrd+1 rda 0 1 0 1 0 1 00 1 0 0 0 00000000 2&nfaw+nrrd+2 d 1 0 0 0 0 1 00 0 0 0 0 - repeat above d command until 2* nfaw + 2* nrrd - 1 12 2*nfaw+2*nrrd repeat sub-loop 10, but ba[2:0] = 2 13 2*nfaw+3*nrrd repeat sub-loop 11, but ba[2:0] = 3 14 2*nfaw+4*nrrd d 1 0 0 0 0 3 00 0 0 0 0 - assert and repeat abov e d command until 3* nfaw - 1, if necessary 15 3*nfaw repeat sub-loop 10, but ba[2:0] = 4 16 3*nfaw+nrrd repeat sub-loop 11, but ba[2:0] = 5 17 3*nfaw+2*nrrd repeat sub-loop 10, but ba[2:0] = 6 18 3*nfaw+3*nrrd repeat sub-loop 11, but ba[2:0] = 7 19 3*nfaw+4*nrrd d 1 0 0 0 0 7 00 0 0 0 0 - assert and repeat abov e d command until 4* nfaw - 1, if necessary a) dm must be driven low all the time. dqs, dqs are used according to rd commands, otherwise mid-level. b) burst sequence driven on each dq signal by read co m mand. outside burst operation, dq signals are mid-level.
rev. 0.3 / jul. 2013 34 idd specifications (tcase: 0 to 95 o c) *module idd values in the datasheet are only a calcul ation based on the component idd spec and register power. the actual measurements may vary according to dq loading cap. 32gb, 4g x 72 lr-d imm: hmt84gl7amr4a 32gb, 4g x 72 lr-d imm: hmt84gl7amr4c symbol montage(c1) inphi(gs02b) unit note ddr3l 1333 ddr3l 1600 ddr3l 1333 ddr3l 1600 idd0 3662 3808 4169 4349 ma idd1 3788 3934 4295 4475 ma idd2n 3374 3520 3881 4061 ma idd2nt 3662 3808 4169 4349 ma idd2p0 946 1020 1527 1633 ma idd2p1 1090 1164 1671 1777 ma idd2q 3446 3520 3953 4061 ma idd3n 4022 4168 4529 4709 ma idd3p 1594 1740 2175 2353 ma idd4r 4436 4744 4943 5285 ma idd4w 4526 4834 5033 5375 ma idd5b 6686 6814 7193 7355 ma idd6 1234 1308 1815 1921 ma idd6et 1522 1596 2103 2209 ma idd7 5426 5644 5933 6185 ma symbol montage(c1) inphi(gs02b) unit note ddr3 1333 ddr3 1600 ddr3 1866 ddr3 1333 ddr3 1600 ddr3 1866 idd0 4213 4351 4490 4855 5045 4949 ma idd1 4339 4495 4652 4981 5189 5111 ma idd2n 3907 4045 4184 4549 4739 4643 ma idd2nt 4195 4405 4544 4837 5099 5003 ma idd2p0 1192 1259 1292 1873 1997 2198 ma idd2p1 1336 1403 1508 2017 2141 2414 ma idd2q 3979 4117 4112 4624 4811 4571 ma idd3n 4555 4765 4904 5197 5459 5363 ma idd3p 1840 1979 2012 2521 2717 2918 ma idd4r 5077 5377 5768 5719 6071 6227 ma idd4w 5167 5467 5858 5809 6161 6317 ma idd5b 7147 7267 7388 7789 7961 7847 ma idd6 1480 1547 1580 2161 2285 2486 ma idd6et 1768 1835 1868 2249 2573 2774 ma idd7 6157 6367 6668 6799 7061 7127 ma
rev. 0.3 / jul. 2013 35 module dimensions 4gx72 - hmt84gl7amr4a(c) 30.00 9.50 17.30 23.30 5.175 detail c detail d 2.10 front 1 120 5.0 1 1 240 121 back 133.35 128.95 memory buffer 4x3.00 010 side max 4.53mm max 0.20 2.50 0.20 1.00 0.80 0.05 detail of contacts c 1.50 0.10 detail of contacts d 0.3 0.15 0.3~0.1 5.00 3.80 2.50 2.50 0.20 3 0.1 1.20 0.15 0.4 13.60 14.90 detail of contacts a detail of contacts b detail a detail b ddp ddp ddp ddp ddp ddp ddp ddp ddp ddp ddp ddp ddp ddp ddp ddp ddp ddp ddp ddp ddp ddp ddp ddp ddp ddp ddp ddp ddp ddp ddp ddp ddp ddp ddp ddp note : 1. tolerance on all dimensions unless otherwise stated. 0.13 ? units: millimeters
rev. 0.3 / jul. 2013 36 4gx72 - hmt84gl7amr4a(c) - heat spreader front 120 back 25.00 registering clock driver 126.4 1.27 010 side max 7.65mm max 1 133.4 2.786 5.1 42.3 26.1 76.6 7.9 34 69.25 3.1 11 119.64 7.4 16 note : 1. tolerance on all dimensions unless otherwise stated. 2.in order to uninstall fdhs, pl ease contact sales administrator. 0.13 ? units: millimeters 30.20 14 7.2 17.0 11.4 120 registering clock driver 1

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